PDS Tech Commercial, Inc. is seeking candidates for an Engineer Digital 3 in Palmdale, CA. If you have experience writing System Verilog and UVM, this is the opportunity you should apply for!
Job Title: Engineer Digital 3
Job Type: Full time; 6 month contract
Schedule: 9x80
Location: Azusa, CA
Pay Rate: $71 per hour
Job Summary
The candidate will be responsible for writing System Verilog and UVM as part of their primary role in the verification of hardware designs written in VHDL. They will work within a Linux environment using TCL scripts to control verification tools and collaborate with RTL designers to resolve test failures. Even Simpler: The job is for someone who writes special computer code to make sure that other computer codes for hardware work correctly without any problems.
Basic Requirements
Bachelor's degree required
Minimum of 5yrs writing System Verilog and UVM as a primary job function
Experience with verification of designs written in VHDL
Experience with Linux command line workflows
Experience writing TCL to control verification tools
Demonstrated ability in root-cause analysis of test failures
Experience working closely with RTL designers to collaboratively resolve verification test failures
Experience with Git SCM using LFS and Submodules
Desired Requirements
10yrs writing System Verilog and UVM as a primary job function
Experience creating prediction models from functional requirements documentation using System Verilog or SystemC
Experience with DPI based simulator interaction for stimulus and prediction
Proficiency scripting in either Perl or Python for parsing and manipulating text files
Experience with Questa Sim and Visualizer
Experience with the UVM-Framework workflow
Experience writing split Class/xRTL BFMs for use with both simulation and Co-Emulation (Veloce experience preferred)
Experience writing and maintaining Verification Plan Documents
Experience working on USG Contracts and the associated documentation/process expectations
Experience with common interface specifications used in spacecraft
Experience verifying designs targeting radiation hardened Virtex FPGAs